DG485 low - power cmos octal analog switch array ? 2014 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en /jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 1 of 6 revised 01/2014 ? 15 volt input range ? on - resistance < 85 ? ? serial data input/output ? low - power (p d < 105 ? w) ? ttl and cmos compatible x any combination of 8 spst to the output ? esd protection > 4000 v ? ? reduced control wires ? reduced board space ? low signal distortion ? reduced switch errors ? reduced power supply ? simple interfacing ? improved reliability ? audio switching and routing ? audio teleconfer encing ? serial data acquisition and process control ? battery and remote systems ? automotive, avionics and ate systems ? summing node amplifiers the dg486 is an analog switch array that may be used as a low power 8 - channel multiplexer for use in serial control applications. any, all or non e of the 8 switches may be closed at any given time. combining low on - resistance (t ds(on) <85 ?) and fast switching ( t on <200 ns), the DG485 is ideally suited for data acquisition, process control, communication, and avionic applications. the control data is input serially into the shift register with each clock pulse. the shift register conten ts can be latched - in via ld at any point into an octal latch which in turn controls all switches. ?? in ) and serial output (d out ) allow cha i ning of arrays f or large systems. built on the high voltage silicon gate process the DG485 has a wide 44 v range. an epitaxial layer prevents latchup. each channel conducts equally well in either direction when on and blocks up to 30 volts peak - to - peak when off. packaging for the dg48 5 consists of the 18 - pin cerdip, plastic dip and 20 - pin plcc for surface mount. temperature ranges available are military, a suffix ( - 55 to 125 o c) and industrial, d suffix ( - 40 to 85 o c). order numbers: cerdip : DG485ak, DG485ak/883 plasti c : DG485dj order number: DG485dn dual - in - line package top view plcc package top view features benefits applications description pin configurations
DG485 low - power cmos octal analog switch array ? 2013 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en/jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 2 of 6 revised 06/2013 spec ifications parameter symbol test conditions unless otherwise specified v+ = 15 v, v - = - 15 v v l = 5 v, v in = 2,4 v, 0.8 v e a suffix - 55 to 125 o c d suffix - 40 to 85 o c unit temp f t yp d min b max b min b max b analog switch analog signal range c v analog full - 15 15 - 15 15 v drain - source on - resistance r ds(on) v+ = 13.5 v, v - = - 13.5 v i s = - 5 ma, v d = 10 v room full 55 85 125 85 125 ? delta drain - source on - resistance ? r ds(on) for each vd : ? r ds(on) = ( ) ( ) ( ) room 6 10 10 % voltage s referenced to v - v+ ................................ ................................ ......................... 44 v gnd ................................ ................................ ..................... 25 v digital inputs 1 v s , v d ................................ . (v - ) - 2 v to (v + ) +2 v or 30 ma, whichever occurs first continuous current (any terminal) ............................. 30 ma current, s or d (pulsed 1 ms, 10% duty cycle) ......... 100 ma storage temperature (a suffix) ................... - 65 to 150 o c (d suffix) .................. - 65 to 125 o c operating temperature (a suffix) ................... - 55 to 125 o c (d suffix) .................. - 40 to 85 o c power dissipation (package)* 18 - pin cerdip** ................................ ........................ 600 mw 18 - pin plasti c dip*** ................................ ................ 470 mw 20 - pin plcc**** ................................ ....................... 450mw * all leads welded or soldered to pc board ** derate 9.2 mw/ o c above 75 o c *** derate 16.5 mw/ o c above 25 o c **** derate 6mw/ o c above 75 o c 1 signals on sx, dx, or inx exceeding v+ or v - will be clamped by internal diodes. limit forward diode current to maximum current ratings. the clk input is edge triggered functional block diagram and truth tables absolute maximum ratings the ld input is level triggered
DG485 low - power cmos octal analog switch array ? 2014 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en /jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 3 of 6 revised 01/2014 spesifications parameter symbol test conditions unless otherwise specified v+ = 15 v, v - = - 15 v v l = 5 v, v in = 2,4 v, 0.8 v e a suffix - 55 to 125 o c d suffix - 40 to 85 o c unit temp f t y p d min b max b min b max b analog switch (contd) switch off leakage current i s(off) v+ = 16.5 v, v - = - 16.5 v room hot 0.01 - 1 - 20 1 20 - 1 - 20 1 20 na i d(off) v d = - 15.6 v, v s = 15.5 v v d = 15.5 v, v s = - 15.5 v room hot 0.1 - 10 - 200 10 200 - 10 - 200 10 200 channel on leakage current id(on) + i s(on) v = 16.5 v v s = v d = 15.5 v one switch at a time room hot 0.11 - 20 - 500 20 500 - 20 - 500 20 500 v = 16.5 v v s = v d = 15.5 v a ll sw itches on room 0.20 input input current with v in low i il v in under test = 0.8 v all other = 2.4 v room hot - 0.00001 - 1 - 5 1 5 - 1 - 5 1 5 ? a input current with v in high i ih v in under test = 2.4 v all other = 0.8 v room hot 0.00001 - 1 - 5 1 5 - 1 - 5 1 5 serial data output output voltage with v in low C d out v ol i o = 1.6 ma, v+ = 4.5 v full 0.25 0.4 0.4 v output voltage with v in high - d out v oh i o = - 8 0 ? a, v + = 16.5 v v l = 4.75 v full 4.4 2.7 2.7 dynamic characteristics turn - on time t on s ee figure 1 v s = 10 v room hot 170 200 275 200 275 ns turn - off time t off see figure 1 v s = 10 v room hot 150 200 275 200 27 6 data setup time t ds see figure 1 room hot 40 60 40 60 data hold time t dh room hot 40 60 40 60 load hold time t lh see figure 1 room hot 100 150 100 150 reset hold time t rm room hot 100 150 100 150 reset ? to clock ? delay t dro room hot 40 60 40 60 charge injection q any one channel v s = 0 v, c l = 1.000 pf room 17 pc off isolation c r l = 50 ?, c l = 5 pf f = 1 mhz, see figure 2 room - 75 db
DG485 low - power cmos octal analog switch array ? 2013 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en/jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 4 of 6 revised 06/2013 spesifications parameter symbol test conditions unless otherwise specified v+ = 15 v, v - = - 15 v v l = 5 v, v in = 2,4 v, 0.8 v e a suffix - 55 to 125 o c d suffix - 40 to 85 o c unit temp f t y p d min b max b min b max b dynamic characteristics source off capacitance c c s(off) vgen = 0 v, rgen = 0 ? f = 1 mhz room 7 pf drain off capacitance c c d(off) room 43 on - state capacitance c c s+d (on) vgen = 0 v, rgen = 0 ? f = 1 mhz, one channel on room 53 vgen = 0 v, rgen = 0 ? f = 1 mhz, all channels on room 122 power supplies positive supply current i+ v+ = 16.5 v, v - = - 16.5 v v in = 0 or 5 v v l = 5.25 v d out open room full 0.001 3 10 3 10 ? a negative supply current i - room fu ll - 0.001 - 3 - 10 - 3 - 10 log ic supply current i l room full 0.001 3 10 3 10 ground current i gnd room full - 0.001 - 3 - 10 - 3 - 10 notes : a. refer to process option flowchart for additional information. b. the algebra ic convention whereby the most nega tive value is a minimum and the most positive a maximum, is used in this data sheet. c. guaranteed by design, not subject to production test. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. vin = input voltage to perf orm proper function. f. room = 25 o c, cold and hot = as determined by the operating temperature suffix. figure 1. switching time test circuit figure 2. adjacent input crosstalk test circuits
DG485 low - power cmos octal analog switch array ? 2014 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en /jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 5 of 6 revised 01/2014 figure 3. off isolation figure 4. = for clk and ld inputs of the same frequency. the recommended phase delay of ld from clk is ? t logic to t logic . t logic (min) : 80 ns at 25 o c v+ = 15 v 15 0 ns at 125 o c v - = - 15 v gnd = 0 v figure 5. multi - function circuit provides input selection, gain ranging and filtering with one DG485 figure 6. non - linear dac circuit applications
DG485 low - power cmos octal analog switch array ? 2013 american microsemiconductor, inc. specifications are subject to change without notice. aerospace mgmt. sys. cert . as/en/jisq9100:2009 rev. c iso9001:2008 cert no. 45325 133 kings road, madison, new jersey 07940 united states of america tel. 1 - 973 - 377 - 9566, fax. 1 - 973 - 377 - 3078 www.americanmicrosemi.com document page 6 of 6 revised 06/2013 figure 7. summing node mixer figure 8. multi - channel sampling and tdm application figure 9. direct serial interface (80 85) applications (contd)
|
